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1 ? fn7018 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved. elantec is a registered trademark of elantec semiconductor, inc. all other trademarks mentioned are the property of their respective owners. EL1881c sync separator, low power the EL1881c video sync separator is manufactured using elantec?s high performance analog cmos process. this device extracts sync timing information from both standard and non-standard video input. it provides composite sync, vertical sync, burst/back porch timing, and odd/even field detection. fixed 70mv sync tip slicing provides sync edge detection when the video input level is between 0.5v p-p and -2v p-p (sync tip amplitude 143mv to 572mv). a single external resistor sets all internal timing to adjust for various video standards. the composite sync output follows video in sync pulses and a vertical sync pulse is output on the rising edge of the first vertical serration following the vertical pre-equalizing string. for non-standard vertical inputs, a default vert ical pulse is output when the vertical signal stays low for longer than the vertical sync default delay time. the odd/even output indicates field polarity detected during the vertical blanking interval. the EL1881c is plug-in compatible with the industry-standard lm1881 and can be substituted for that part in 5v applications with lower required supply current. the EL1881c is available in the 8-pin pdip and so packages and is specified for op eration over the full -40c to +85c temperature range. features ntsc, pal, secam, non-standard video sync separation fixed 70mv slicing of video input levels from 0.5v p-p to 2v p-p low supply current - 1.5ma typ. single +5v supply composite, vertical sync output odd/even field output burst/back porch output available in 8-pin pdip and so packages applications video amplifiers pcmcia applications a/d drivers line drivers portable computers high-speed communications rgb applications broadcast equipment active filtering demo board a dedicated demo board is available. pinout EL1881c (8-pin pdip, so) top view ordering information part no. package tape & reel pkg. no. EL1881cn 8-pin pdip - mdp0031 EL1881cs 8-pin so - mdp0027 EL1881cs-t7 8-pin so 7? mdp0027 EL1881cs-t13 8-pin so 13? mdp0027 composite sync out composite video in vertical sync out gnd v dd 5v odd/even output r set bust/back porch output 1 2 3 4 8 7 6 5 data sheet september 16, 2002
2 absolute maximum ratings (t a = 25c) v cc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc +0.5v operating ambient temperature range . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mw caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications v dd = 5v, t a = 25c, r set = 681k ? , unless otherwise specified. parameter description min typ max unit i dd , quiescent v dd = 5v 0.75 1.5 3 ma clamp voltage pin 2, i load = -100a 1.35 1.5 1.65 v clamp discharge current pin 2 = 2v 6 12 16 a clamp charge current pin 2 = 1v -1.3 -1 0.7 ma r set pin reference voltage pin 6 1.1 1.22 1.35 v v ol output low voltage i ol = 1.6ma 0.24 0.5 v v oh output high voltage i oh = -40a 4 4.8 v i oh = -1.6ma 3 4.6 dynamic specifications parameter description min typ max unit comp sync prop delay, t cs see figure 2 20 35 75 ns vertical sync width, t vs normal or default tr igger, 50%-50% 190 230 300 s vertical sync default delay, t vsd see figure 3 35 62 85 s burst/back porch delay, t bd see figure 2 120 200 300 ns burst/back porch width, t b see figure 2 2.5 3.5 4.5 s input dynamic range video input amplitude to maintain 50% slice spec 0.5 2 v p-p slice level v slice /v clamp 55 70 85 mv EL1881c
3 pin descriptions pin number pin name pin function 1 composite sync out composite sync pulse output; sync pulses start on a falling edge and end on a rising edge 2 composite video in ac coupled composite video input; sy nc tip must be at the lowest potential (positive picture phase) 3 vertical sync out vertical sync pulse output; the falling edge of vert sync is the start of the vertical period 4 gnd supply ground 5 burst/back porch output burst/back porch output; low during bur st portion of composite video 6 rset (note 1) an external resistor to ground sets all internal timing; a 681k 1% resistor w ill provide correct timing for ntsc signals 7 odd/even output odd/even field output; high dur ing odd fields, low during even fields; transitions occur at start of vert sync pulse 8 vdd 5v positive supply (5v) note: 1. r set must be a 1% resistor EL1881c
4 typical performance curves supply current vs temperature r set =681k ? 1.65 1.6 1.5 1.45 1.4 1.35 -50 -25 25 75 100 temperature (c) supply current (ma) 5.5v 4.5v 5v v clamp voltage vs temperature r set =681k ? 1.535 1.515 1.505 1.495 1.485 temperature (c) v clamp (v) v rset vs temperature r set =681k ? 1.24 1.23 1.22 1.21 1.2 temperature (c) v rset (v) clamp charge current vs temperature r set =681k ? 1.1 1 0.9 0.85 temperature (c) clamp charge current (ma) clamp discharge current vs temperature r set =681k ? 11.4 11.3 11.2 10.9 10.8 10.7 temperature (c) clamp discharge current (a) 1.525 11 1.05 0.95 1.55 0 50 -50 -25 25 75 100 050 -50 -25 25 75 100 050 -50 -25 25 75 100 050 -50 -25 25 75 100 050 5.5v 5v 4.5v 5.5v 5v 4.5v 5.5v 5v 4.5v 5.5v 4.5v 5v 11.1 1.235 1.225 1.215 1.205 r set vs horizontal frequency 1000 600 200 0 10 15 25 35 40 45 frequency (khz) r set (k ? ) 800 400 20 30 EL1881c
5 typical performance curves (continued) vertical default delay vs r set v dd =5v, t a =25c 120 100 60 40 20 0 200 400 600 800 1000 r set (k ? ) vertical sync default delay (s) burst/back porch wi dth vs temperature 3.9 3.8 3.6 3.3 3.1 temperature (c) burst/back porch width (s) composite sync prop delay vs temperature 41 31 -50 -25 0 50 100 temperature (c) composite sync prop delay (ns) 80 35 33 3.4 3.2 3.7 3.5 25 75 -50 -25 0 50 100 25 75 5.5v 5v 4.5v 39 37 vertical sync width vs r set v dd =5v, t a =25c 350 100 50 0 200 400 600 1000 r set (k ? ) vertical sync width (s) 250 300 150 800 200 burst/back porch width vs r set v dd =5v, t a =25c 6 5 4 3 2 1 200 400 600 800 1000 r set (k ? ) burst width (s) burst/back porch delay vs r set v dd =5v, t a =25c 350 150 100 50 0 200 400 800 1000 r set (k ? ) burst/back porch delay (ns) 200 300 600 250 EL1881c
6 typical performance curves (continued) composite sync to odd/even delay time r set =681k ? 27 25 21 17 15 -50-25 0 255075100 temperature (c) t cs-oe (ns) 23 19 5.5v 4.5v 5v package power dissipation vs ambient temp. jedec jesd51-3 low effective thermal conductivity 1.4 1.2 0.6 0.2 0 0 255075100125150 ambient temperature (c) power dissipation (w) 0.8 0.4 1 85 781mw 1.25w j a = 1 0 0 c / j a = 1 6 0 c / p d i p 8 s o 8 burst/back porch delay vs temperature r set =681k ? 250 200 150 100 50 0 -50 -25 0 50 100 temperature (c) burst/back porch delay (ns) vertical sync pulse width vs temperature r set =681k ? 239 235 233 231 229 -50 -25 25 75 100 temperature (c) vertical sync pulse width (s) composite sync to vert ical sync delay time r set =681k ? 20 16 14 12 10 -50 -25 0 50 100 temperature (c) t cs-vs (ns) vertical sync default de lay time vs temperature r set =681k ? 64.5 60.5 59.5 temperature (c) vertical sync defa ult delay time (s) 18 237 63.5 62.5 61.5 5.5v 4.5v 5v 5.5v 4.5v 5v 25 75 5.5v 4.5v 5v 5.5v 4.5v 5v 25 75 0 50 -50 -25 0 50 100 25 75 EL1881c
7 timing diagrams notes: b. the composite sync output reproduces all the video input sync pulses, with a propagation delay. c. vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. d. odd-even output is low for ev en field, and high for odd field. e. back porch goes low for a fi xed pulse width on the trailing edge of video input sync pulses. note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). * signal 1a drawing reproduced with permission from eia. figure 1. standard (ntsc input) timing EL1881c
8 expanded timing diagrams figure 2. standard vertical timing figure 3. non-standard vertical timing EL1881c
9 applications information video in a simplified block diagram is shown following page. an ac coupled video signal is input to video in pin 2 via , c 1 nominally 0.1f. clamp charge current will prevent the signal on pin 2 from going any more negative than sync tip ref, about 1.5v. this charge current is nominally about 1ma. a clamp discharge current of about 10a is always attempting to discharge c 1 to sync tip ref, thus charge is lost between sync pulses that must be replaced during sync pulses. the droop voltage that will occur can be calculated from it = cv, where v is the droop voltage, i is the discharge current, t is the time between sync pulses (sync period - sync tip width), and c is c 1 . an ntsc video signal has a horizontal frequency of 15.73khz, and a sync tip width of 4.7s. this gives a period of 63.6s and a time t = 58.9s. the droop voltage will then be v = 5.9mv. this is less than 2% of a nominal sync tip amplitude of 286mv. the char ge represented by this droop is replaced in a time given by t = cv/i, where i = clamp charge current = 1ma. here t = 590ns, about 12% of the sync pulse width of 4.7s. it is important to choose c 1 large enough so that the droop voltage does not approach the switching threshold of the internal comparator. fixed gain buffer the clamped video signal then passes to the fixed gain buffer which places the sync slice level at the equivalent level of 70mv above sync tip. the output of this buffer is presented to the comparator, along with the slice reference. the comparator output is le vel shifted and buffered to ttl levels, and sent out as composite sync to pin 1. burst a low-going burst pulse follows each rising edge of sync, and lasts approximately 3.5s for an r set of 681k ? . figure 4. standard (ntsc input) h. sync detail EL1881c
10 vertical sync a low-going vertical sync puls e is output during the start of the vertical cycle of the incomi ng video signal. the vertical cycle starts with a pre-equaliz ing phase of pulses with a duty cycle of about 93%, followed by a vertical serration phase that has a duty cycle of about 15%. vertical sync is clocked out of the EL1881c on the first rising edge during the vertical serration phase. in the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 60s after the last falling edge of the vertical equalizing phase for r set = 681k ? . odd/even because a typical television picture is composed of two interlaced fields, there is an odd field that includes all the odd lines, and an even field that consists of the even lines. this odd/even field information is decoded by the EL1881c during the end of picture information and the beginning of vertical information. the odd/even circuit includes a t-flip- flop that is reset during full horizontal lines, but not during half lines or vertical equalization pulses. the t-flip-flop is clocked during each falling edge of these half hperiod pulses. even fields will toggle until a low state is clocked to the odd/even pin 7 at the beginning of vertical sync, and odd fields will cause a high state to be clocked to the odd/even pin at the start of the next ve rtical sync pulse. odd/even can be ignored if using non-interlaced video, as there is no change in timing from one field to the next. r set an external r set resistor, connected from r set pin 6 to ground, produces a reference current that is used internally as the timing reference for vertical sync width, vertical sync default delay, burst gate delay and burst width. decreasing the value of r set increases the reference current, which in turn decreases reference times and pulse widths. a higher frequency video input necessitates a lower r set value. chroma filter a chroma filter is suggested to increase the s/n ratio of the incoming video signal. use of th e optional chroma filter is shown in figure 5. it can be implemented very simply and inexpensively with a series resistor of 620 ? and a parallel capacitor of 500pf, which gives a single pole roll-off frequency of about 500khz. this sufficiently attenuates the 3.58mhz (ntsc) or 4.43mhz (pal) color burst signal, yet passes the approximately 15khz sync signals without appreciable attenuation. a chroma filter will increase the propagation delay from the co mposite input to the outputs. figure 5. EL1881c
11 simplified block diagram - + burst vert sync odd/even ref gen 1 5 3 7 6 4 2 8 r f 620 ? c f 510pf c 1 0.1f c 3 0.1f r set * sync tip 70mv slice composite video in g nd r set note: * r set must be at 1% resistor composite sync burst/back porch out vertical sync out odd/even v dd 5v v dd c 2 0.1f clamp comp. slice 1.57v sync tip ref 1.5v figure 6. EL1881c all intersil u.s. products are manufactured, a ssembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.int ersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com

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